Robust Low Power VLSI

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J. F. Ryan and Calhoun, B. H., “A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS”, in Custom Integrated Circuits Conference (CICC), 2010.

J. F. Ryan and Calhoun, B. H., “Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation”, in International Symposium on Quality Electronic Design, 2008, pp. 127-132.

J. F. Ryan, Wang, J., and Calhoun, B. H., “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design”, in GLSVLSI, 2007, pp. 275-280.