Robust Low Power VLSI

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A. Roy, Klinefelter, A., Yahya, F., Chen, X., Gonzalez, P., Lukas, C. J., Akella, D., Boley, J., Craig, K., Faisal, M., Oh, S., Roberts, N., Shakhsheer, Y., Shrivastava, A., Vasudevan, D., Wentzloff, D. D., and Calhoun, B., “A 6.45μW Self-Powered SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems”, IEEE Transactions on Biomedical Circuits and Systems, vol. 9, pp. 862-874, 2015.

S. Gupta, Truesdell, D. S., and Calhoun, B. H., “A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.

A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)

X. Liu, Agrawal, A., Tanaka, A., and Calhoun, B. H., “A 6nA Fully-Autonomous Triple-Input Hybrid-Inductor-Capacitor Multi-Output Power Management System with Multi-Rail Energy Sharing, All-Rail Cold Startup, and Adaptive Conversion Control for mm-scale Distributed Systems”, in 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024.

A_6nA_Fully Autonomous_Triple-Input_Hybrid-Inductor-Capacitor_Multi-Output_Power_Management_System_with_Multi-Rail_Energy_Sharing_All-Rail_Cold_Startup_and_Adaptive_Conve.pdf (1.55 MB)

D. S. Truesdell, Breiholz, J., Kamineni, S., Liu, N. X., Magyar, A., and Calhoun, B. H., “A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic”, IEEE Solid-State Circuits Letters (SSCL), 2019.

A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)

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A. Roy and Calhoun, B. H., “A 71% Efficient Energy Harvesting and Power Management Unit for Sub-µW Power Biomedical Applications”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.

S. Li and Calhoun, B. H., “A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×105 Dynamic Load Range, 99.99% Current Efficiency, and 2mV Output Voltage Ripple”, in IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, 2019.

J. Moody, Bassirian, P., Roy, A., Liu, N. X., Pancrazio, S., N. Barker, S., Calhoun, B. H., and Bowers, S. M., “A -76dBm 7.4 nW wakeup radio with automatic offset compensation”, in International Solid-State Circuits Conference (ISSCC), 2018.

P. Wang, Agarwala, R., Bishop, H. L., Dissanayake, A., and Calhoun, B. H., “A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.

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X. Liu, Li, S., and Calhoun, B. H., “An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control”, in 2021 IEEE European Solid-State Circuits Conference (ESSCIRC), 2021.

An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control.pdf (580.42 KB)

J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., “An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End”, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.

S. Li, Breiholz, J., Kamineni, S., Im, J., Wentzloff, D. D., and Calhoun, B. H., “An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction”, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.

R. Agarwala, Wang, P., Tanneeru, A., Lee, B., Misra, V., and Calhoun, B. H., “An 88.6nW Ozone Pollutant Sensing Interface IC with a 159 dB Dynamic Range”, in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020.

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Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., “A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V”, in Custom Integrated Circuits Conference, San Jose, 2011.

S. Li, Liu, X., and Calhoun, B. H., “A 956pW Switched-Capacitor Sub-Bandgap Reference with 0.44-to-3.3V Supply Range, -67dB PSRR, and 0.2% within-Wafer Inaccuracy for Nanowatt IoT Systems”, in 2022 IEEE European Solid-State Circuits Conference (ESSCIRC), 2022.

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X. Chen, Breiholz, J., Yahya, F. B., Lukas, C. J., Kim, H. - S., Calhoun, B. H., and Wentzloff, D. D., “Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 Frequency Edge Combiner”, IEEE Journal of Solid-State Circuits, 2019.

J. F. Ryan, Khanna, S., and Calhoun, B. H., “An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal”, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.

J. F. Ryan, Wang, J., and Calhoun, B. H., “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design”, in GLSVLSI, 2007, pp. 275-280.

J. Wang, Nalam, S., and Calhoun, B. H., “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.

B. H. Calhoun and Chandrakasan, A., “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS”, in European Solid-State Circuits Conference, 2005, pp. 363-366.

J. Boley, Wang, J., and Calhoun, B. H., “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.

J. Boley, Wang, J., and Calhoun, B. H., “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN”, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.

J. Boley, Calhoun, B. H., and Wang, J., “Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”. 2011.

H. L. Bishop, Wang, P., and Calhoun, B. H., “Application-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systems”, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.

S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.

S. Nalam and Calhoun, B. H., “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.

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