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“Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS”, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
, “An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
, “An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches”, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
, “Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT”, in HOT Chips, 2015.
, “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.
, “Using island-style bi-directional intra-CLB routing in low-power FPGAs”, in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.
, “Using synchronized oscillators to compute the maximum independent set”, Nature Communications, 2020.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization”, Transactions of Very Large Scale Integration Systems, 2015.
, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
, “What is a Body Sensor Network?”, ACM / SIGDA Newsletter, vol. 41, 2011.
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