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Conference Paper
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., A battery-less 507nW SoC with integrated platform power manager and SiP interfaces, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., A battery-less 507nW SoC with integrated platform power manager and SiP interfaces, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC, in ISSCC, San Francisco, 2012.
F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC, in ISSCC, San Francisco, 2012.
S. Kamineni, Sharma, A., Harjani, R., Sapatnekar, S. S., and Calhoun, B. H., AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells, in Design, Automation and Test in Europe Conference (DATE), 2023, 2023.PDF icon AuxcellGen-A Framework for Autonomous Generation of Analog and Memory Unit Cells.pdf (3.37 MB)
S. Nalam and Calhoun, B. H., Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T, in CICC, 2009, pp. 709-712.
S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation, in ISQED, 2010, pp. 139-146.
S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation, in ISQED, 2010, pp. 139-146.
H. L. Bishop, Wang, P., and Calhoun, B. H., Application-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systems, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
B. H. Calhoun and Chandrakasan, A., Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS, in European Solid-State Circuits Conference, 2005, pp. 363-366.
B. H. Calhoun and Chandrakasan, A., Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS, in European Solid-State Circuits Conference, 2005, pp. 363-366.
J. Wang, Nalam, S., and Calhoun, B. H., Analyzing Static and Dynamic Write Margin for Nanometer SRAMs, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
J. F. Ryan, Wang, J., and Calhoun, B. H., Analyzing and Modeling Process Balance for Sub-threshold Circuit Design, in GLSVLSI, 2007, pp. 275-280.
J. F. Ryan, Khanna, S., and Calhoun, B. H., An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
S. Li, Liu, X., and Calhoun, B. H., A 956pW Switched-Capacitor Sub-Bandgap Reference with 0.44-to-3.3V Supply Range, -67dB PSRR, and 0.2% within-Wafer Inaccuracy for Nanowatt IoT Systems, in 2022 IEEE European Solid-State Circuits Conference (ESSCIRC), 2022.
Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V, in Custom Integrated Circuits Conference, San Jose, 2011.
Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V, in Custom Integrated Circuits Conference, San Jose, 2011.
R. Agarwala, Wang, P., Tanneeru, A., Lee, B., Misra, V., and Calhoun, B. H., An 88.6nW Ozone Pollutant Sensing Interface IC with a 159 dB Dynamic Range, in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020.
S. Li, Breiholz, J., Kamineni, S., Im, J., Wentzloff, D. D., and Calhoun, B. H., An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
A. Tanaka, He, S., Mounesi, R., Liu, X., Faruqe, O., Mim, N. Gahan, Truesdell, D. S., Nasiri, A., and Calhoun, B. H., An 81.0% Peak Efficiency, 1.0W/cm^3 Miniaturized 5V/1A AC-DC Converter using a Highly-Integrated Primary-Side Active Clamp Flyback Controller with Adaptive Frequency and Zero-Voltage Switching, in 2025 IEEE Custom Integrated Circuits Conference (CICC), In Press.
X. Liu, Li, S., and Calhoun, B. H., An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control, in 2021 IEEE European Solid-State Circuits Conference (ESSCIRC), 2021.PDF icon An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control.pdf (580.42 KB)
P. Wang, Agarwala, R., Bishop, H. L., Dissanayake, A., and Calhoun, B. H., A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
J. Moody, Bassirian, P., Roy, A., Liu, N. X., Pancrazio, S., N. Barker, S., Calhoun, B. H., and Bowers, S. M., A -76dBm 7.4 nW wakeup radio with automatic offset compensation, in International Solid-State Circuits Conference (ISSCC), 2018.

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