Publications
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, “Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy”, in SRC Techcon, 2012.
, “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.
, “Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy”, CASES. 2011.
, “Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception”, in Conference on the Biology of Marine Mammals, 2011.
, “Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception”, in Conference on the Biology of Marine Mammals, 2011.
, “New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm”, in ISQED, 2011.
, “Non-Random Device Mismatch Considerations in Nanoscale SRAM”, IEEE Transactions of VLSI Systems (TVLSI), 2011.
, “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication”, in Design Automation and Test in Europe (DATE), 2011.
, “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.
, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
, “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.
, “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization”, in TECHCON, 2009.
, “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.
, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
, “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.