Robust Low Power VLSI

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Journal Article

S. Gupta and Calhoun, B. H., “Dynamic Write V_MIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.

Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)

S. Gupta and Calhoun, B. H., “Dynamic Read V_MIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.

Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)

X. Liu, Agrawal, A., Tanaka, A., and Calhoun, B. H., “Distributed Energy Harvesting and Power Management Units for Self-Powered In-Fabric Sensing Networks”, 2024 IEEE Midwest Symposium on Circuits and Systems (MWSCAS), invited paper, 2024.

B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.

P. Beshay, Ryan, J. F., and Calhoun, B. H., “A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers”, Journal of Low Power Electronics and Applications, 2013.

B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.

E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., “Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks”, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.

A. Shrivastava and Calhoun, B. H., “A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications”, 2013.

X. Chen, Alghaihab, A., Shi, Y., Truesdell, D. S., Calhoun, B. H., and Wentzloff, D. D., “A Crystal-Less BLE Transmitter with Clock Recovery from GFSK-Modulated BLE Packets”, IEEE Journal of Solid-State Circuits, 2021.

S. Z. Ahmed, Truesdell, D. S., Tan, Y., Calhoun, B. H., and Ghosh, A. W., “A comprehensive analysis of Auger generation impacted planar Tunnel FETs”, Solid-State Electronics, 2020.

B. H. Calhoun and Brooks, D., “Can Subthreshold and Near-Threshold Circuits Go Mainstream?”, IEEE Micro, vol. 30, pp. 80-85, 2010.

B. H. Calhoun, Lach, J., Stankovic, J., Wentzloff, D. D., Whitehouse, K., Barth, A., Brown, J. K., Li, Q., Oh, S., Roberts, N., and Zhang, Y., “Body Sensor Networks: A Holistic Approach From Silicon to Users”, IEEE Proceedings, 2011.

Y. Zhang, Zhang, F., Shakhsheer, Y., Silver, J. D., Klinefelter, A., Nagaraju, M., Boley, J., Pandey, J., Shrivastava, A., Carlson, E. J., Wood, A., Calhoun, B. H., and Otis, B. P., “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.

D. S. Truesdell, Breiholz, J., Kamineni, S., Liu, N. X., Magyar, A., and Calhoun, B. H., “A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic”, IEEE Solid-State Circuits Letters (SSCL), 2019.

A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)

S. Nalam and Calhoun, B. H., “5T SRAM with Asymmetric Sizing for Improved Read Stability”, JSSC, 2011.

K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.

B. H. Calhoun and Chandrakasan, A., “A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.

N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., and Calhoun, B. H., “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time”, IEEE Journal of Solid-State Circuits (JSSC), 2019.

A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., “A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2021.

P. Wang, Agarwala, R., Ownby, N., Liu, X., and Calhoun, B. H., “A 2.3-5.7μW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2 , and Pulse Transit Time Co-Monitoring”, IEEE Transactions on Biomedical Circuits and Systems, 2024.

X. Shen, Duvvuri, D., Bassirian, P., Bishop, H. L., Liu, X., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A 184 nW, -78.3 dBm Sensitivity Antenna-Coupled Supply, Temperature, and Interference-Robust Wake-up Receiver at 4.9 GHz”, IEEE Transactions on Microwave Theory and Techniques, 2022.

O. Faruqe, Lee, D., Ownby, N., and Calhoun, B. H., “A 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub-μW Robust Wearable Sensing”, IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 4, 2024.

L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLL”, IEEE Open Journal of the Solid-State Circuits Society, 2024.

R. Agarwala, Wang, P., Bishop, H. L., Dissanayake, A., and Calhoun, B. H., “A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, IEEE Journal of Solid-State Circuits, 2021.

D. S. Truesdell, Dissanayake, A., and Calhoun, B. H., “A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability”, IEEE Solid-State Circuits Letters (SSCL), 2019.

A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)

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