Publications
Export 84 results:
Author Title [ Type
] Year Filters: First Letter Of Last Name is S [Clear All Filters]
, “Dark vs. Dim Silicon and Near-Threshold Computing”, in Dark Silicon Workshop (DaSi), 2012.
, “Energy-Efficient Link Layer for Wireless Microsensor Networks”, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
, “Fast Algorithm for Clock Grid Simulation”, in European Solid State Circuits Conference (ESSCIRC), 2002, pp. 771-774.
, “Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems”, in International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.
, “Graph Coloring using Coupled Oscillator-based Dynamical Systems”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
, “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.
, “A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Cracow, Poland, 2019.
, “Modeling DC-DC Converter Efficiency and Power Management in Ultra Low Power Systems”, in Subthreshold Microelectronics Conference, 2012.
, “MSN: Memory Sensor for NBTI”, in Techcon, 2009.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation”, in International Symposium on Low Power Electronics and Design, 2012.
, “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation”, in Subthreshold Microelectronics Conference, 2011.
, “A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs”, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
, “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
, “Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design”, in International Conference on VLSI Design, India, 2008, pp. 131-136.
, “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication”, in Design Automation and Test in Europe (DATE), 2011.
, “Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy”, in SRC Techcon, 2012.
, “Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy”, in SRC Techcon, 2012.
, “REESES: Rapid Efficient Energy Scalable ElectronicS”, in GOMAC Tech, 2010.
, “A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs”, in International Symposium on Quality Electronic Design (ISQED), 2014.
, “SRAM-Based NBTI/PBTI Sensor System Design”, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.