Robust Low Power VLSI
VLSI Design Group

Navigation

Search This Site

Publications

Export 92 results:
Author Title [ Type(Desc)] Year
Filters: First Letter Of Last Name is L  [Clear All Filters]
Conference Paper
J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., “An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End”, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
S. Li, Breiholz, J., Kamineni, S., Im, J., Wentzloff, D. D., and Calhoun, B. H., “An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction”, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
R. Agarwala, Wang, P., Tanneeru, A., Lee, B., Misra, V., and Calhoun, B. H., “An 88.6nW Ozone Pollutant Sensing Interface IC with a 159 dB Dynamic Range”, in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020.
Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., “A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V”, in Custom Integrated Circuits Conference, San Jose, 2011.
S. Li, Liu, X., and Calhoun, B. H., “A 956pW Switched-Capacitor Sub-Bandgap Reference with 0.44-to-3.3V Supply Range, -67dB PSRR, and 0.2% within-Wafer Inaccuracy for Nanowatt IoT Systems”, in 2022 IEEE European Solid-State Circuits Conference (ESSCIRC), 2022.
S. Li, Liu, X., and Calhoun, B. H., “A 956pW Switched-Capacitor Sub-Bandgap Reference with 0.44-to-3.3V Supply Range, -67dB PSRR, and 0.2% within-Wafer Inaccuracy for Nanowatt IoT Systems”, in 2022 IEEE European Solid-State Circuits Conference (ESSCIRC), 2022.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
A. Shrivastava, Lach, J., and Calhoun, B., “A Charge Pump Based Receiver Circuit for a Voltage Scaled Interconnect”, in International Symposium on Low Power Electronics and Design, 2012.
N. Liu and Calhoun, B. H., “Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “FAR: A 4.12uW Ferro-electric Auto-Recovery for Battery-less BSN SoCs”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
P. Sotiriadis, Franza, O., Bailey, D., Calhoun, B., Lin, D., and Chandrakasan, A., “Fast Algorithm for Clock Grid Simulation”, in European Solid State Circuits Conference (ESSCIRC), 2002, pp. 771-774.
H. L. Bishop, Wang, P., Fan, D., Lach, J., and Calhoun, B. H., “Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy HarvestingEmbedded Systems”, in Global Internet of Things Summit (GIoTS), 2018.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., “Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-Low Power Systems”, in 2017 IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2017.
D. S. Truesdell, Liu, X., Breiholz, J., Gupta, S., Li, S., and Calhoun, B. H., “NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling”, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022.PDF icon NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
D. S. Truesdell, Liu, X., Breiholz, J., Gupta, S., Li, S., and Calhoun, B. H., “NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling”, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022.PDF icon NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
M. Putic, Di, L., Calhoun, B. H., and Lach, andJohn, “Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design”, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
S. Li, Roy, A., and Calhoun, B. H., “A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
L. Di, Putic, M., Lach, J., and Calhoun, B. H., “Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling”, in International Conference on Computer Design, pages 605-611, 2008.
K. Craig, Shakhsheer, Y., Khanna, S., Arrabi, S., Lach, J., Calhoun, B. H., and Kosonocky, S., “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
B. H. Meyer, Skadron, K., George, N., Calhoun, B. H., and Lach, J., “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication”, in Design Automation and Test in Europe (DATE), 2011.
L. Szafaryn, Chen, J., Calhoun, B. H., Lach, J., Skadron, K., and Meyer, B. H., “Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy”, in SRC Techcon, 2012.
B. H. Calhoun, Arrabi, S., Khanna, S., Shakhsheer, Y., Craig, K., Ryan, J., and Lach, J., “REESES: Rapid Efficient Energy Scalable ElectronicS”, in GOMAC Tech, 2010.

Pages