Publications
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, “Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications”, in International Symposium on Circuits and Systems (ISCAS), 2015.
, “Flexible Circuits and Architectures for Ultra Low Power”, Proceedings of the IEEE, vol. 98, pp. 267-282, 2010.
, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.
, “MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros”, in IEEE Custom Integrated Circuits Conference (CICC), 2021.
kamineni2021.pdf (9.26 MB)
kamineni2021.pdf (9.26 MB), “Micropower Wireless Sensors”, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.
, “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.
, “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.
, “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.
, “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation”, in Subthreshold Microelectronics Conference, 2011.
, “Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories”, in VLSI Design Conference, 2014.
, “A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs”, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
, “A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC”, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, p. 941, 2012.
, “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
, “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
, “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
, “REESES: Rapid Efficient Energy Scalable ElectronicS”, in GOMAC Tech, 2010.
, “A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber”, in IEEE International Solid-State Circuits Conference (ISSCC), 2023. 15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB)
15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB), “Serial Sub-threshold Circuits for Ultra-Low-Power Systems”, in International Symposium on Low Power Electronics and Design, 2009.
, “Stepped Supply Voltage Switching for Energy Constrained Systems”, in ISQED, 2011.