Robust Low Power VLSI
VLSI Design Group

Navigation

Search This Site

Publications

Export 34 results:
Author [ Title(Asc)] Type Year
Filters: First Letter Of Last Name is D  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
1
J. Moody, Dissanayake, A., Bishop, H., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
J. Moody, Dissanayake, A., Bishop, H., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR”, in IEEE Custom Integrated Circuits Conference (CICC), 2023.
L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR”, in IEEE Custom Integrated Circuits Conference (CICC), 2023.
L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLL”, IEEE Open Journal of the Solid-State Circuits Society, 2024.
L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLL”, IEEE Open Journal of the Solid-State Circuits Society, 2024.
0
N. Gilbert, Zhang, Y., Dinh, J., Calhoun, B., and Hollmer, S., “A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications”, in Symposium on VLSI Circuits, 2013.
R. Agarwala, Wang, P., Bishop, H. L., Dissanayake, A., and Calhoun, B. H., “A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, IEEE Journal of Solid-State Circuits, 2021.
D. S. Truesdell, Dissanayake, A., and Calhoun, B. H., “A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability”, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)

Pages