Robust Low Power VLSI
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A. Shrivastava, Akella, D., and Calhoun, B. H., “A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, 2016.
X. Shen, Duvvuri, D., Bassirian, P., Bishop, H. L., Liu, X., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A 184 nW, -78.3 dBm Sensitivity Antenna-Coupled Supply, Temperature, and Interference-Robust Wake-up Receiver at 4.9 GHz”, IEEE Transactions on Microwave Theory and Techniques, 2022.
X. Liu, Kamineni, S., Breiholz, J., Calhoun, B. H., and Li, S., “A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization”, in IEEE International Solid-State Circuits Conference (ISSCC), 2022.PDF icon A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB)
X. Liu, Chen, Z., Mim, N. Gahan, Agrawal, A., and Calhoun, B. H., “A 1pJ/Bit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks”, in 2023 IEEE Biomedical Circuits and Systems Conference, 2023.PDF icon A 1pJbit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks.pdf (2.54 MB)
X. Liu, Chen, Z., Mim, N. Gahan, Agrawal, A., and Calhoun, B. H., “A 1pJ/Bit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks”, in 2023 IEEE Biomedical Circuits and Systems Conference, 2023.PDF icon A 1pJbit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks.pdf (2.54 MB)
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D. Akella, Shrivastava, A., and Calhoun, B. H., “A 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 V”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Rohnert Park, CA, 2015.
P. Wang, Agarwala, R., Ownby, N., Liu, X., and Calhoun, B. H., “A 2.3-5.7μW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2 , and Pulse Transit Time Co-Monitoring”, IEEE Transactions on Biomedical Circuits and Systems, 2024.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., “A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2021.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., Chen, X., Wentzloff, D. D., and Calhoun, B. H., “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., Chen, X., Wentzloff, D. D., and Calhoun, B. H., “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., and Calhoun, B. H., “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time”, IEEE Journal of Solid-State Circuits (JSSC), 2019.
B. H. Calhoun and Chandrakasan, A., “A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
B. H. Calhoun and Chandrakasan, A., “A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
A. Banerjee, Liu, N., Patel, H. N., and Calhoun, B. H., “A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors”, in 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, 2017.
B. H. Calhoun and Chandrakasan, A., “A 256kb Sub-threshold SRAM in 65nm CMOS”, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
B. H. Calhoun and Chandrakasan, A., “A 256kb Sub-threshold SRAM in 65nm CMOS”, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
S. Jocke, Bolus, J., Wooters, S. N., Jurik, A. D., Weaver, A. F., Blalock, T. N., and Calhoun, B. H., “A 2.6-μW Sub-threshold Mixed-signal ECG SoC”, in Symposium on VLSI Circuits, 2009.
A. Agrawal, Chen, Z., Desman, B. E., Wang, J., Tanaka, A., Foysal, F., Hess, C. D., Farrell, W., Owens, J., Truesdell, D. S., and Calhoun, B. H., “A 2-Dimensional mm-scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6mm x 2.15mm SoC and bySPI chiplets”, in 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025.
A. Agrawal, Chen, Z., Desman, B. E., Wang, J., Tanaka, A., Foysal, F., Hess, C. D., Farrell, W., Owens, J., Truesdell, D. S., and Calhoun, B. H., “A 2-Dimensional mm-scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6mm x 2.15mm SoC and bySPI chiplets”, in 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025.
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K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.
K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.
S. Li, Liu, X., and Calhoun, B. H., “A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy Harvesting and Power Management Platform with 1.2×10^5 Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-Up”, in IEEE International Solid-State Circuits Conference (ISSCC), 2022.
A. Shrivastava, Craig, K., Roberts, N., Wentzloff, D. D., and Calhoun, B. H., “A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems”, in EEE International Solid-State Circuits Conference (ISSCC), 2015.

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