Publications
] , “A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations”, in Custom Integrated Circuits Conference (CICC), San Jose, CA, 2015.
, “A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications”, in 32nd International Conference on VLSI Design, 2019.
, “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
, “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.