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D. S. Truesdell and Calhoun, B. H., Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
D. S. Truesdell and Calhoun, B. H., A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution, in IEEE Custom Integrated Circuits Conference (CICC) 2019, Austin, TX, 2019.PDF icon A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB)
D. S. Truesdell and Calhoun, B. H., Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
D. S. Truesdell, Breiholz, J., Kamineni, S., Liu, N. X., Magyar, A., and Calhoun, B. H., A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
D. S. Truesdell, Dissanayake, A., and Calhoun, B. H., A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
D. S. Truesdell, Li, S., and Calhoun, B. H., A 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/°C Stability Using a Duty-Cycled Digital Frequency-Locked Loop, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.PDF icon A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
D. S. Truesdell, Ahmed, S. Z., Ghosh, A. W., and Calhoun, B. H., Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020.PDF icon Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
D. S. Truesdell and Calhoun, B. H., A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range, IEEE Solid-State Circuits Letters (SSCL), 2020.PDF icon A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
D. S. Truesdell, Li, S., and Calhoun, B. H., A 0.5V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator with 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop, IEEE Journal of Solid-State Circuits, 2021.PDF icon A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB)