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Author Title [ Type(Desc)] Year
Filters: Author is Anantha Chandrakasan  [Clear All Filters]
Conference Paper
B. H. Calhoun and Chandrakasan, A., A 256kb Sub-threshold SRAM in 65nm CMOS, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
B. H. Calhoun and Chandrakasan, A., Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS, in European Solid-State Circuits Conference, 2005, pp. 363-366.
B. H. Calhoun and Chandrakasan, A., Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits, in International Symposium on Low Power Electronics and Design, 2004, pp. 90-95.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., Design Methodology for Fine-Grained Leakage Control in MTCMOS, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
B. H. Calhoun, Wang, A., and Chandrakasan, A., Device Sizing for Minimum Energy Operation in Subthreshold Circuits, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
E. Shih, Calhoun, B. H., Cho, S. - H., and Chandrakasan, A., Energy-Efficient Link Layer for Wireless Microsensor Networks, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
P. Sotiriadis, Franza, O., Bailey, D., Calhoun, B., Lin, D., and Chandrakasan, A., Fast Algorithm for Clock Grid Simulation, in European Solid State Circuits Conference (ESSCIRC), 2002, pp. 771-774.
B. Calhoun and Chandrakasan, A., Standby Voltage Scaling for Reduced Power, in Custom Integrated Circuits Conference (CICC), 2003, pp. 639-642.
B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., Sub-threshold Design: The Challenges of Minimizing Circuit Energy, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., Ultra-Dynamic Voltage Scaling for Energy Starved Electronics, in Proc. of GOMAC Tech, 2007.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
Journal Article
B. H. Calhoun and Chandrakasan, A., A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., Design Considerations for Ultra-low Energy Wireless Microsensor Nodes, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., A Leakage Reduction Methodology for Distributed MTCMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.
B. H. Calhoun, Wang, A., and Chandrakasan, A., Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 2005.
B. H. Calhoun and Chandrakasan, A., Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.
B. H. Calhoun and Chandrakasan, A., Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.