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D. S. Truesdell, Li, S., and Calhoun, B. H., A 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/°C Stability Using a Duty-Cycled Digital Frequency-Locked Loop, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.PDF icon A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
D. S. Truesdell, Dissanayake, A., and Calhoun, B. H., A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
D. S. Truesdell, Breiholz, J., Kamineni, S., Liu, N. X., Magyar, A., and Calhoun, B. H., A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
D. S. Truesdell and Calhoun, B. H., A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range, IEEE Solid-State Circuits Letters (SSCL), 2020.PDF icon A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
D. S. Truesdell and Calhoun, B. H., A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution, in IEEE Custom Integrated Circuits Conference (CICC) 2019, Austin, TX, 2019.PDF icon A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB)
D. S. Truesdell, Li, S., and Calhoun, B. H., A 0.5V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator with 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop, IEEE Journal of Solid-State Circuits, 2021.PDF icon A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB)
D. S. Truesdell and Calhoun, B. H., Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
D. S. Truesdell, Liu, X., Breiholz, J., Gupta, S., Li, S., and Calhoun, B. H., NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022.PDF icon NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
D. S. Truesdell and Calhoun, B. H., Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
D. S. Truesdell, Ahmed, S. Z., Ghosh, A. W., and Calhoun, B. H., Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020.PDF icon Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
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L. Szafaryn, Chen, J., Calhoun, B. H., Lach, J., Skadron, K., and Meyer, B. H., Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy, in SRC Techcon, 2012.
J. B. Stocking, Eberhardt, W. C., Shakhsheer, Y. A., Paulus, J. R., Appleby, M., and Calhoun, B. H., A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing, in IEEE Sensors, 2010.
P. Sotiriadis, Franza, O., Bailey, D., Calhoun, B., Lin, D., and Chandrakasan, A., Fast Algorithm for Clock Grid Simulation, in European Solid State Circuits Conference (ESSCIRC), 2002, pp. 771-774.
A. Singhee, Wang, J., Calhoun, B. H., and Rutenbar, R. A., Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design, in International Conference on VLSI Design, India, 2008, pp. 131-136.
A. Shrivastava and Calhoun, B. H., Modeling DC-DC Converter Efficiency and Power Management in Ultra Low Power Systems, in Subthreshold Microelectronics Conference, 2012.
A. Shrivastava and Calhoun, B. H., A sub-threshold clock and data recovery circuit for a wireless sensor node. 2011.
A. Shrivastava, Pandey, J., Otis, B., and Calhoun, B. H., A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node, in VLSI Design Conference, 2013.
A. Shrivastava, Roberts, N. E., Khan, O. U., Wentzloff, D. D., and Calhoun, B. H., A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting with 220mV Cold-Start and -14.5dBm, 915MHz RF Kick-Start, IEEE Journal of Solid-State Circuits (JSSC), vol. 50, pp. 1820-1832, 2015.

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