Robust Low Power VLSI
VLSI Design Group

Navigation

Search This Site

Publications

Export 6 results:
Author Title Type [ Year(Asc)]
Filters: First Letter Of Title is S and Author is B. H. Calhoun  [Clear All Filters]
2016
F. Yahya, Patel, H., Boley, J., Banerjee, A., and Calhoun, B. H., “A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
2015
J. Boley and Calhoun, B. H., “Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset”, in International Symposium on Quality Electronic Design, 2015.
2014
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., “Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM”, in Design Automation Conference (DAC), 2014.
2011
Y. Yu, Huang, J., Khanna, S., Calhoun, B. H., Lach, J., Shelat, A., and Evans, D., “A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm”. 2011 Workshop on RFID Security, 2011.
2009
M. Bhargava, Nalam, S., Calhoun, B. H., and Mai, K., “An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization”, in TECHCON, 2009.
B. H. Calhoun, Khanna, S., Mann, R., and Wang, J., “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.