Robust Low Power VLSI
VLSI Design Group

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Author Title Type [ Year(Asc)]
Filters: First Letter Of Title is E and Author is Benton H. Calhoun  [Clear All Filters]
2016
H. Qi, Ayorinde, O., and Calhoun, B. H., “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.
2013
C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
2011
Y. Zhang, Shakhsheer, Y., Barth, A. T., Powell, Jr., H. C., Ridenour, S. A., Hanson, M. A., Lach, J., and Calhoun, B. H., “Energy Efficient Design for Body Sensor Nodes”, Journal of Low Power Electronics and Applications, 2011.
J. Wang, Hoefler, A., and Calhoun, B. H., “An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction”, Transactions on VLSI Systems (TVLSI), 2011.
2010
S. N. Wooters, Calhoun, B. H., and Blalock, T. N., “An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
2008
J. Wang and Calhoun, B. H., “An Enhanced Adaptive Canary System for SRAM Standby Power Reduction”, in TECHCON, 2008.
2001
E. Shih, Calhoun, B. H., Cho, S. - H., and Chandrakasan, A., “Energy-Efficient Link Layer for Wireless Microsensor Networks”, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.