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Author Title Type [ Year(Desc)]
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2003
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., Design Methodology for Fine-Grained Leakage Control in MTCMOS, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
2006
B. H. Calhoun and Chandrakasan, A., A 256kb Sub-threshold SRAM in 65nm CMOS, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., Low Energy Digital Circuit Design, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.
A. P. Chandrakasan, Verma, N., Kwong, J., Daly, D., Ickes, N., Finchelstein, D., and Calhoun, B. H., Micropower Wireless Sensors, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.
B. H. Calhoun, ,, and Chandrakasan, A., Power Gating and Dynamic Voltage Scaling, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
B. H. Calhoun and Chandrakasan, A., Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.
B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., Sub-threshold Design: The Challenges of Minimizing Circuit Energy, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
2008
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.

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