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A. Mallick, Bashar, M. K., Truesdell, D. S., Calhoun, B. H., Joshi, S., and Shukla, N., Using synchronized oscillators to compute the maximum independent set, Nature Communications, 2020.
H. Qi, Ayorinde, O., and Calhoun, B. H., An Ultra-Low-Power FPGA for IoT Applications, in S3S 2017, 2017.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., Ultra-Dynamic Voltage Scaling for Energy Starved Electronics, in Proc. of GOMAC Tech, 2007.
A. Banerjee and Calhoun, B. H., An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell, in S3S, Monterey, CA, 2013.
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B. H. Calhoun, Khanna, S., Zhang, Y., Ryan, J., and Otis, B., System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.
H. N. Patel, Yahya, F. B., and Calhoun, B. H., Subthreshold SRAM: Challenges, Design Decisions, and Solutions, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
P. Beshay, Ryan, J. F., and Calhoun, B. H., Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry, in Subthreshold Microelectronics Conference, 2012.
B. H. Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors, in International Symposium on Circuits and Systems, 2009.
J. F. Ryan and Calhoun, B. H., A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS, in Custom Integrated Circuits Conference (CICC), 2010.
B. H. Calhoun, Zhang, Y., Khanna, S., Craig, K., Shakhsheer, Y., and Lach, J., A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic, in GOMAC Tech, 2011.
B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., Sub-threshold Design: The Challenges of Minimizing Circuit Energy, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
A. Shrivastava and Calhoun, B. H., A sub-threshold clock and data recovery circuit for a wireless sensor node. 2011.
X. Liu, Calhoun, B. H., and Li, S., A Sub-nW 93% Peak Efficiency Buck Converter with Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control, IEEE Journal of Solid-State Circuits, 2022.PDF icon A SubnW 93 Peak Efficiency Buck Converter With Wide Dynamic Range Fast DVFS and Asynchronous Load Transient Control.pdf (3.94 MB)
S. Li and Calhoun, B. H., Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations, in 2020 IEEE Custom Integrated Circuits Conference (CICC), (invited paper), 2020.
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.
B. H. Calhoun and Chandrakasan, A., Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.
J. Wang and Calhoun, B. H., Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.

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