Publications
Export 169 results:
Author [ Title
] Type Year Filters: Author is Benton H. Calhoun [Clear All Filters]
, βA 0.36 mmΒ² On-the-Fly I2C-to-SPI Converter for E-Textile Applicationsβ, in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), In Press.
, βA 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systemsβ, in International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015.
, βA 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosisβ, Journal of Low Power Electronics and Applications (JLPEA), 2018.
, βA 0.5V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator with 96.1-ppm/Β°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loopβ, IEEE Journal of Solid-State Circuits, 2021.
A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB)
A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB), βA 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/Β°C Stability Using a Duty-Cycled Digital Frequency-Locked Loopβ, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB), βA 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/Β°C Stabilityβ, IEEE Solid-State Circuits Letters (SSCL), 2019. A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB), βA 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoringβ, IEEE Journal of Solid-State Circuits, 2021.
, βA -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLLβ, IEEE Open Journal of the Solid-State Circuits Society, 2024.
, βA -102dBm Sensitivity, 2.2Β΅A Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIRβ, in IEEE Custom Integrated Circuits Conference (CICC), 2023.
, βA -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiverβ, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, βA -108dBm Sensitivity, -28dB SIR, 130nW to 41ΞΌW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiverβ, in IEEE Custom Integrated Circuits Conference (CICC), 2020.
, βA 10-Channel, 1.2 Β΅W, Reconfigurable Capacitanceto-Digital Converter for Low-Power, Wearable Healthcare Applicationsβ, in 2023 IEEE Biomedical Circuits and Systems Conference, 2023.
, βA 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub-ΞΌW Robust Wearable Sensingβ, IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 4, 2024.
, βA 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variationsβ, in Custom Integrated Circuits Conference (CICC), San Jose, CA, 2015.
, βA 150nW, 5ppm/oC, 100kHz On-Chip Clock Source for Ultra Low Power SoCsβ, in Custom Integrated Circuits Conference, San Jose, 2012.
, βA 184 nW, -78.3 dBm Sensitivity Antenna-Coupled Supply, Temperature, and Interference-Robust Wake-up Receiver at 4.9 GHzβ, IEEE Transactions on Microwave Theory and Techniques, 2022.
, βA 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimizationβ, in IEEE International Solid-State Circuits Conference (ISSCC), 2022. A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB)
A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB), βA 1pJ/Bit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networksβ, in 2023 IEEE Biomedical Circuits and Systems Conference, 2023. A 1pJbit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks.pdf (2.54 MB)
A 1pJbit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks.pdf (2.54 MB), βA 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 Vβ, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Rohnert Park, CA, 2015.
, βA 2.3-5.7ΞΌW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2 , and Pulse Transit Time Co-Monitoringβ, IEEE Transactions on Biomedical Circuits and Systems, 2024.
, βA 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiverβ, IEEE Journal of Solid-State Circuits, 2021.
, βA 2.5 ppm/Β°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 Β΅s Start-Up Timeβ, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
, βA 2.5 ppm/Β°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Timeβ, IEEE Journal of Solid-State Circuits (JSSC), 2019.
, βA 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operationβ, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
, βA 256kb Sub-threshold SRAM in 65nm CMOSβ, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.