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Author Title [ Type(Desc)] Year
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Conference Paper
A. Shrivastava, Wentzloff, D., and Calhoun, B. H., A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting, in IEEE Custom Integrated Circuits Conference (CICC), 2014.
A. Shrivastava, Ramadass, Y. K., Khanna, S., Bartling, S., and Calhoun, B. H., A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages, in Symposium on VLSI Circuits, 2014.
Y. Huang, Shrivastava, A., and Calhoun, B. H., A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
A. Banerjee, Liu, N., Patel, H. N., and Calhoun, B. H., A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors, in 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, 2017.
A. Shrivastava, Craig, K., Roberts, N., Wentzloff, D. D., and Calhoun, B. H., A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems, in EEE International Solid-State Circuits Conference (ISSCC), 2015.
H. N. Patel, Roy, A., Yahya, F. B., Liu, N., Kumeno, K., Yasuda, M., Harada, A., Ema, T., and Calhoun, B. H., A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic, in European Solid State Circuits Conference (ESSCIRC), 2016.
Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V, in Custom Integrated Circuits Conference, San Jose, 2011.
J. F. Ryan, Khanna, S., and Calhoun, B. H., An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
J. Wang, Nalam, S., and Calhoun, B. H., Analyzing Static and Dynamic Write Margin for Nanometer SRAMs, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation, in ISQED, 2010, pp. 139-146.
S. Nalam and Calhoun, B. H., Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T, in CICC, 2009, pp. 709-712.
W. C. Eberhardt, Shakhsheer, Y. A., and Calhoun, B. H., A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability, in IEEE Sensors, Limrick, Ireland, 2011.
J. B. Stocking, Eberhardt, W. C., Shakhsheer, Y. A., Paulus, J. R., Appleby, M., and Calhoun, B. H., A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing, in IEEE Sensors, 2010.
N. Liu and Calhoun, B. H., Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
S. Nalam, Chandra, V., Aitken, R. C., and Calhoun, B. H., Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM, in Design Automation and Test Europe (DATE), 2011.
A. Klinefelter, Ryan, J., Tschanz, J., and Calhoun, B. H., Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications, in International Symposium on Circuits and Systems (ISCAS), 2015.
Y. Zhang and Calhoun, B. H., Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits, in International Symposium on Quality Electronic Design (ISQED), 2014.
S. Arrabi, Moore, D., Wang, L., Skadron, K., and Calhoun, B. H., Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems, in International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.
J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress, in CICC, San Jose, CA, 2010.
J. J. Granacki, Calhoun, B. H., Dasu, A. R., Jagasivamani, M., McIlrath, L., and Fritze, M., LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications, in GOMAC Tech, 2014.
D. Kamakshi, Fojtik, M., Khailany, B., Kudva, S., Zhou, Y., and Calhoun, B. H., Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks, in ASYNC, 2016.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B. H., Modeling SRAM Dynamic VMIN, in International Conference on IC Design and Technology (ICICDT), 2014.
S. Khanna, Nalam, S. V., and Calhoun, B. H., Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories, in VLSI Design Conference, 2014.
A. Klinefelter and Calhoun, B. H., A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs, in S3S Conference, Monterey, CA, 2014.