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A. D. Kamakshi, Shrivastava, A., and Calhoun, B. H., “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.

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A. Shrivastava, Roberts, N. E., Khan, O. U., Wentzloff, D. D., and Calhoun, B. H., “A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting with 220mV Cold-Start and -14.5dBm, 915MHz RF Kick-Start”, IEEE Journal of Solid-State Circuits (JSSC), vol. 50, pp. 1820-1832, 2015.

A. Shrivastava, Wentzloff, D., and Calhoun, B. H., “A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting”, in IEEE Custom Integrated Circuits Conference (CICC), 2014.

A. Shrivastava, Ramadass, Y. K., Khanna, S., Bartling, S., and Calhoun, B. H., “A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages”, in Symposium on VLSI Circuits, 2014.

Y. Huang, Shrivastava, A., and Calhoun, B. H., “A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.

A. Shrivastava, Akella, D., and Calhoun, B. H., “A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, 2016.

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N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.

A. Banerjee, Liu, N., Patel, H. N., and Calhoun, B. H., “A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors”, in 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, 2017.

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A. Shrivastava, Craig, K., Roberts, N., Wentzloff, D. D., and Calhoun, B. H., “A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems”, in EEE International Solid-State Circuits Conference (ISSCC), 2015.

D. Akella, Shrivastava, A., Duan, C., and Calhoun, B. H., “A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 6, 2016.

J. .Bolus, Calhoun, B. H., and .Blalock, T., “39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 16, 2014.

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H. N. Patel, Roy, A., Yahya, F. B., Liu, N., Kumeno, K., Yasuda, M., Harada, A., Ema, T., and Calhoun, B. H., “A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic”, in European Solid State Circuits Conference (ESSCIRC), 2016.

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Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., “A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V”, in Custom Integrated Circuits Conference, San Jose, 2011.

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J. F. Ryan, Khanna, S., and Calhoun, B. H., “An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal”, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.

J. Wang, Nalam, S., and Calhoun, B. H., “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.

J. Boley, Wang, J., and Calhoun, B. H., “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN”, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.

J. Boley, Wang, J., and Calhoun, B. H., “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.

J. Boley, Calhoun, B. H., and Wang, J., “Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”. 2011.

S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.

S. Nalam and Calhoun, B. H., “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.

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W. C. Eberhardt, Shakhsheer, Y. A., and Calhoun, B. H., “A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability”, in IEEE Sensors, Limrick, Ireland, 2011.

M. A. Hanson, Jr, H. C. Powell, Barth, A. T., Ringgenberg, K., Calhoun, B. H., Aylor, J. H., and Lach, J., “Body Area Sensor Networks: Challenges and Opportunities”, Computer, vol. 42, pp. 58–65, 2009.

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J. B. Stocking, Eberhardt, W. C., Shakhsheer, Y. A., Paulus, J. R., Appleby, M., and Calhoun, B. H., “A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing”, in IEEE Sensors, 2010.

B. H. Meyer, Calhoun, B. H., Lach, J. C., and Skadron, K., “Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy”, CASES. 2011.

Y. Shakhsheer, Zhang, Y., Otis, B., and Calhoun, B. H., “A Custom Processor for Node and Power Management of a Battery-less Body Sensor Node in 130nm CMOS”, Custom Integrated Circuits Conference. San Jose, 2012.

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