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2019
C. J. Lukas, Yahya, F. B., Breiholz, J., Roy, A., Chen, X., Patel, H. N., Liu, N. X., Kosari, A., Li, S., Kamakshi, D. Akella, Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications, IEEE Transactions on Biomedical Circuits and Systems, 2019.PDF icon 08625544.pdf (3.22 MB)
J. Moody, Dissanayake, A., Bishop, H., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., and Calhoun, B. H., A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time, IEEE Journal of Solid-State Circuits (JSSC), 2019.
D. S. Truesdell, Breiholz, J., Kamineni, S., Liu, N. X., Magyar, A., and Calhoun, B. H., A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
J. Moody, Dissanayake, A., Bishop, H. L., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
J. Moody, Bassirian, P., Roy, A., Liu, N. X., N Barker, S., Calhoun, B. H., and Bowers, S. M., Interference Robust Detector-First Near-Zero Power Wake-Up Receiver, IEEE Journal of Solid-State Circuits, 2019.