VLSI Design Group


Search This Site


Export 8 results:
Author Title [ Type(Desc)] Year
Filters: Author is S. Khanna  [Clear All Filters]
Conference Paper
A. Shrivastava, Ramadass, Y. K., Khanna, S., Bartling, S., and Calhoun, B. H., A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages, in Symposium on VLSI Circuits, 2014.
Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V, in Custom Integrated Circuits Conference, San Jose, 2011.
J. F. Ryan, Khanna, S., and Calhoun, B. H., An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
S. Khanna, Nalam, S. V., and Calhoun, B. H., Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories, in VLSI Design Conference, 2014.
B. H. Calhoun, Arrabi, S., Khanna, S., Shakhsheer, Y., Craig, K., Ryan, J., and Lach, J., REESES: Rapid Efficient Energy Scalable ElectronicS, in GOMAC Tech, 2010.
B. H. Calhoun, Khanna, S., Mann, R., and Wang, J., Sub-threshold Circuit Design with Shrinking CMOS Devices, in International Symposium on Circuits and Systems, 2009.