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J. Wang and Calhoun, B. H., Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations, Transactions on VLSI Systems (TVLSI), 2011.
R. Mann and Calhoun, B., New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm, in ISQED, 2011.
R. W. Mann, Hook, T. B., Nguyen, P., and Calhoun, B. H., Non-Random Device Mismatch Considerations in Nanoscale SRAM, IEEE Transactions of VLSI Systems (TVLSI), 2011.
K. Craig, Shakhsheer, Y., Khanna, S., and Calhoun, B. H., Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation, in Subthreshold Microelectronics Conference, 2011.
A. M. Klinefelter and Calhoun, B. H., A Programmable Multi-channel Sub-threshold FIR Filter for a Body Area Sensor Node. 2011.
B. H. Meyer, Skadron, K., George, N., Calhoun, B. H., and Lach, J., Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication, in Design Automation and Test in Europe (DATE), 2011.
S. Khanna, Craig, K., Shakhsheer, Y., Arrabi, S., Lach, J., and Calhoun, B., Stepped Supply Voltage Switching for Energy Constrained Systems, in ISQED, 2011.
Y. Yu, Huang, J., Khanna, S., Calhoun, B. H., Lach, J., Shelat, A., and Evans, D., A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm. 2011 Workshop on RFID Security, 2011.
A. Shrivastava and Calhoun, B. H., A sub-threshold clock and data recovery circuit for a wireless sensor node. 2011.
B. H. Calhoun, Zhang, Y., Khanna, S., Craig, K., Shakhsheer, Y., and Lach, J., A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic, in GOMAC Tech, 2011.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., Tracking On-Chip Age Using Distributed, Embedded Sensors, Transactions on VLSI Systems (TVLSI), 2011.
B. H. Calhoun and Lach, J., What is a Body Sensor Network?, ACM / SIGDA Newsletter, vol. 41, 2011.
S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation, in ISQED, 2010, pp. 139-146.
B. H. Calhoun and Brooks, D., Can Subthreshold and Near-Threshold Circuits Go Mainstream?, IEEE Micro, vol. 30, pp. 80-85, 2010.
J. B. Stocking, Eberhardt, W. C., Shakhsheer, Y. A., Paulus, J. R., Appleby, M., and Calhoun, B. H., A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing, in IEEE Sensors, 2010.
S. N. Wooters, Calhoun, B. H., and Blalock, T. N., An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores, in TECHCON, 2010.
B. H. Calhoun, Ryan, J., Khanna, S., Putic, M., and Lach, J., Flexible Circuits and Architectures for Ultra Low Power, Proceedings of the IEEE, vol. 98, pp. 267-282, 2010.
R. W. Mann, Wang, J., Nalam, S., Khanna, S., Braceras, G., Pilo, H., and Calhoun, B. H., Impact of circuit assist methods on margin and performance in 6T SRAM, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.
J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress, in CICC, San Jose, CA, 2010.
, Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM, in ISQED, 2010, pp. 1-8.
B. H. Calhoun, Arrabi, S., Khanna, S., Shakhsheer, Y., Craig, K., Ryan, J., and Lach, J., REESES: Rapid Efficient Energy Scalable ElectronicS, in GOMAC Tech, 2010.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., SRAM-Based NBTI/PBTI Sensor System Design, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
J. Wang and Calhoun, B. H., Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.
J. F. Ryan and Calhoun, B. H., A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS, in Custom Integrated Circuits Conference (CICC), 2010.