%0 Journal Article %J IEEE Transactions on Circuits and Systems I: Regular Papers %D 2021 %T Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs %A Shourya Gupta %A Benton H. Calhoun %B IEEE Transactions on Circuits and Systems I: Regular Papers %8 12/2020 %G eng %U https://ieeexplore.ieee.org/document/9309185 %R 10.1109/TCSI.2020.3044836 %0 Journal Article %J IEEE Transactions on Circuits and Systems I: Regular Papers %D 2021 %T Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs %A Shourya Gupta %A Benton H. Calhoun %B IEEE Transactions on Circuits and Systems I: Regular Papers %G eng %0 Conference Paper %B 32nd International Conference on VLSI Design %D 2019 %T A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications %A Arijit Banerjee %E Benton H. Calhoun %B 32nd International Conference on VLSI Design %8 01/2019 %G eng %0 Conference Paper %B ISLPED %D 2014 %T A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM %A Peter Beshay %A Vikas Chandra %A Robert Aitken %A Benton H. Calhoun %B ISLPED %8 08/2014 %G eng %0 Journal Article %D 2013 %T A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications %A Aatmesh Shrivastava %A Benton H. Calhoun %X This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and power management strategies cannot be correctly established without accounting for the associated overhead related to the DC-DC converters that provide regulated power to the system. The proposed model accurately predicts the efficiency of inductor based DC-DC converters with varying topologies and control schemes across a range of output voltage and current loads. It also accounts for the energy and timing overhead associated with the change in the operating condition of the regulator. Since modern SoCs employ power management techniques that vary the voltage and current loads seen by the converter, accurate modeling of the impact on the converter efficiency becomes critical. We use this model to compute the overall cost of two power distribution strategies for a SoC with multiple voltage islands. The proposed model helps us to obtain the energy benefits of a power management technique and can also be used as a basis for comparison between power management techniques or as a tool for design space exploration early in a SoC design cycle. %8 06/2013 %G eng %U http://www.mdpi.com/2079-9268/3/3/215 %1 jlpea-03-00215-v2 (5).pdf|jlpea-03-00215-v2 (5).pdf %0 Journal Article %J Journal of Low Power Electronics and Applications %D 2013 %T A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers %A Peter Beshay %A Joseph F. Ryan %A Benton H. Calhoun %B Journal of Low Power Electronics and Applications %8 05/2013 %G eng %U http://www.mdpi.com/2079-9268/3/2/159 %9 Journal Article %1 Beshay_JLPEA13.pdf|Beshay_JLPEA13.pdf %0 Conference Paper %B Dark Silicon Workshop (DaSi) %D 2012 %T Dark vs. Dim Silicon and Near-Threshold Computing %A Liang Wang %A Kevin Skadron %A Benton H. Calhoun %B Dark Silicon Workshop (DaSi) %8 06/2012 %G eng %0 Book %B The Modular Series of Microelectronic Device & Circuit Design, eds. C. Sodini and R. Howe %D 2012 %T Design Principles for Digital CMOS Integrated Circuit Design %A Benton H. Calhoun %B The Modular Series of Microelectronic Device & Circuit Design, eds. C. Sodini and R. Howe %I NTS Press %8 03/2012 %@ 978-1-934891-14-8 %G eng %0 Journal Article %J Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law) %D 2008 %T Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS %A Benton H. Calhoun %A Yu Cao, Xin Li %A Ken Mai %A Lawrence T. Pileggi %A Rob A. Rutenbar %A Kenneth L. Shepard %B Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law) %V 96 %P 343-365 %8 02/2008 %G eng %1 CalhounEtAl_IEEEProc_08.pdf|CalhounEtAl_IEEEProc_08.pdf %0 Journal Article %J IEEE Transactions on Computers %D 2005 %T Design Considerations for Ultra-low Energy Wireless Microsensor Nodes %A Benton H. Calhoun %A Denis D. Daly %A Naveen Verma %A Daniel Finchelstein %A David D. Wentzloff %A Alice Wang %A Seong-Hwan Cho %A Anantha Chandrakasan %B IEEE Transactions on Computers %V 54 %P 727-740 %8 06/2005 %G eng %1 TransComp_fromIEEExplore.pdf|TransComp_fromIEEExplore.pdf %0 Journal Article %J Journal of VLSI Signal Processing %D 2004 %T Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks %A Eugene Shih %A Seong-Hwan Cho %A Fred S. Lee %A Benton H. Calhoun %A Anantha Chandrakasan %B Journal of VLSI Signal Processing %V 37 %P 77-94 %8 05/2004 %G eng %1 FinalJVLSISigProc04.pdf|FinalJVLSISigProc04.pdf %0 Conference Paper %B International Conference on VLSI Design %D 2004 %T Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes %A David D. Wentzloff %A Benton H. Calhoun %A Rex Min %A Alice Wang %A Nathan Ickes %A Anantha P. Chandrakasan %B International Conference on VLSI Design %P 361-367 %8 01/2004 %G eng %1 2004_Wentzloff_VLSI_Design.pdf|2004_Wentzloff_VLSI_Design.pdf %0 Conference Paper %B Custom Integrated Circuits Conference (CICC) %D 2004 %T Device Sizing for Minimum Energy Operation in Subthreshold Circuits %A Benton H. Calhoun %A Alice Wang %A Anantha Chandrakasan %B Custom Integrated Circuits Conference (CICC) %P 95-98 %8 10/2004 %G eng %1 2004_Calhoun_CICC_1.pdf|2004_Calhoun_CICC_1.pdf %0 Conference Paper %B International Symposium on Low Power Electronics and Design (ISLPED) %D 2003 %T Design Methodology for Fine-Grained Leakage Control in MTCMOS %A Benton H. Calhoun %A Frank A. Honore %A Anantha Chandrakasan %B International Symposium on Low Power Electronics and Design (ISLPED) %P 104-109 %8 08/2003 %G eng %1 2003_Calhoun_ISLPED.pdf|2003_Calhoun_ISLPED.pdf