%0 Conference Paper %B European Solid State Circuits Conference (ESSCIRC) %D 2016 %T A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic %A H. N. Patel %A Roy, A. %A F. B. Yahya %A N. Liu %A K. Kumeno %A M. Yasuda %A A. Harada %A T. Ema %A B. H. Calhoun %B European Solid State Circuits Conference (ESSCIRC) %G eng %1 A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf|A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf