TY - CONF T1 - An Open-source Framework for Autonomous SoC Design with Analog Block Generation T2 - 28th IFIP/IEEE International Conference on Very Large Scale Integration Y1 - 2020 A1 - Tutu Ajayi A1 - Sumanth Kamineni A1 - Yaswanth K Cherivirala A1 - Morteza Fayazi A1 - Kyumin Kwon A1 - Mehdi Saligane A1 - Shourya Gupta A1 - Chien-Hen Chen A1 - Dennis Sylvester A1 - David Blaauw A1 - Ronald Dreslinski Jr A1 - Benton Calhoun A1 - David D. Wentzloff KW - analog generator KW - analog synthesis KW - SoC generator JF - 28th IFIP/IEEE International Conference on Very Large Scale Integration CY - Salt Lake City, UT, USA. (Nominated for Best Paper Award) ER - TY - CONF T1 - Optimizing SRAM Bitcell Reliability and Energy for IoT Applications T2 - International Symposium on Quality Electronic Design (ISQED) Y1 - 2016 A1 - Harsh Patel A1 - Farah Yahya A1 - Benton Calhoun JF - International Symposium on Quality Electronic Design (ISQED) PB - IEEE CY - Santa Clara, CA U1 - Optimizing SRAM Bitcell Reliability and Energy for IoT Applications.pdf|Optimizing SRAM Bitcell Reliability and Energy for IoT Applications.pdf ER - TY - CONF T1 - Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs T2 - 2015 25th International Conference on Field Programmable Logic and Applications (FPL) Y1 - 2015 A1 - He Qi A1 - Oluseyi Ayorinde A1 - Yu Huang A1 - Benton Calhoun JF - 2015 25th International Conference on Field Programmable Logic and Applications (FPL) CY - London, UK U1 - Optimizing Energy Efficient Low-Swing Interconnect for Sub-threshold FPGAs.pdf|Optimizing Energy Efficient Low-Swing Interconnect for Sub-threshold FPGAs.pdf ER -