TY - JOUR T1 - A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption JF - IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper) Y1 - 2019 A1 - Jesse Moody A1 - Anjana Dissanayake A1 - Henry L Bishop A1 - Ruochen Lu A1 - NingXi Liu A1 - Divya Duvvuri A1 - Anming Gao A1 - Daniel S. Truesdell A1 - N. Scott Barker A1 - Songbin Gong A1 - Benton H. Calhoun A1 - Steven M. Bowers ER - TY - CONF T1 - Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method T2 - S3S Conference Y1 - 2013 A1 - Yanqing Zhang A1 - Benton H. Calhoun JF - S3S Conference CY - Monterey, California U1 - Zhang_S3S2013.pdf|Zhang_S3S2013.pdf ER -