TY - JOUR T1 - A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs JF - J. Low Power Electron. Appl. (JLPEA) Y1 - 2016 A1 - F. Yahya A1 - H. Patel A1 - Boley, J. A1 - A. Banerjee A1 - B. H. Calhoun VL - 6 U1 - A Sub-threshold 8T SRAM Macro with 12.29nWKB Standby Power and 6.24 pJaccess for Battery-Less IoT SoCs.pdf|A Sub-threshold 8T SRAM Macro with 12.29nWKB Standby Power and 6.24 pJaccess for Battery-Less IoT SoCs.pdf ER - TY - CONF T1 - Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset T2 - International Symposium on Quality Electronic Design Y1 - 2015 A1 - Boley, J. A1 - B. H. Calhoun JF - International Symposium on Quality Electronic Design ER - TY - CONF T1 - Modeling SRAM Dynamic VMIN T2 - International Conference on IC Design and Technology (ICICDT) Y1 - 2014 A1 - Boley, J. A1 - V. Chandra A1 - R. Aitken A1 - B. H. Calhoun JF - International Conference on IC Design and Technology (ICICDT) ER - TY - JOUR T1 - Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN JF - Journal of Low Power Electronics and Applications (JLPEA) Y1 - 2012 A1 - Boley, J. A1 - J. Wang A1 - B. H. Calhoun VL - 2 U1 - Boley_JLPEA2012.pdf|Boley_JLPEA2012.pdf ER - TY - ABST T1 - Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin Y1 - 2011 A1 - Boley, J. A1 - B. H. Calhoun A1 - J. Wang ER -