TY - CONF T1 - A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic T2 - European Solid State Circuits Conference (ESSCIRC) Y1 - 2016 A1 - H. N. Patel A1 - Roy, A. A1 - F. B. Yahya A1 - N. Liu A1 - K. Kumeno A1 - M. Yasuda A1 - A. Harada A1 - T. Ema A1 - B. H. Calhoun JF - European Solid State Circuits Conference (ESSCIRC) U1 - A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf|A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf ER -