TY - CONF T1 - A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors T2 - 2017 IEEE Custom Integrated Circuits Conference (CICC) Y1 - 2017 A1 - A. Banerjee A1 - N. Liu A1 - H. N. Patel A1 - B. H. Calhoun ED - J. Poulton ED - C. T. Gray JF - 2017 IEEE Custom Integrated Circuits Conference (CICC) CY - Austin, TX, 2017 U1 - CICC2017_SRAM.pdf|Banerjee_CICC2017.pdf ER - TY - CONF T1 - A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic T2 - European Solid State Circuits Conference (ESSCIRC) Y1 - 2016 A1 - H. N. Patel A1 - Roy, A. A1 - F. B. Yahya A1 - N. Liu A1 - K. Kumeno A1 - M. Yasuda A1 - A. Harada A1 - T. Ema A1 - B. H. Calhoun JF - European Solid State Circuits Conference (ESSCIRC) U1 - A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf|A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic.pdf ER -