TY - JOUR T1 - A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers JF - Journal of Low Power Electronics and Applications Y1 - 2013 A1 - Peter Beshay A1 - Joseph F. Ryan A1 - Benton H. Calhoun UR - http://www.mdpi.com/2079-9268/3/2/159 U1 - Beshay_JLPEA13.pdf|Beshay_JLPEA13.pdf ER - TY - CONF T1 - Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry T2 - Subthreshold Microelectronics Conference Y1 - 2012 A1 - Peter Beshay A1 - Joseph F. Ryan A1 - Benton H. Calhoun JF - Subthreshold Microelectronics Conference U1 - Beshay_DAZ_subVT12_paper.pdf|Beshay_DAZ_subVT12_paper.pdf ER - TY - CONF T1 - A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS T2 - Custom Integrated Circuits Conference (CICC) Y1 - 2010 A1 - Joseph F. Ryan A1 - Benton H. Calhoun JF - Custom Integrated Circuits Conference (CICC) U1 - Ryan_CICC2010.pdf|Ryan_CICC2010.pdf ER - TY - CONF T1 - Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation T2 - International Symposium on Quality Electronic Design Y1 - 2008 A1 - Joseph F. Ryan A1 - Benton H. Calhoun JF - International Symposium on Quality Electronic Design U1 - Ryan_ISQED2008_slides.pdf|Ryan_ISQED2008_slides.pdf ER - TY - CONF T1 - Analyzing and Modeling Process Balance for Sub-threshold Circuit Design T2 - GLSVLSI Y1 - 2007 A1 - Joseph F. Ryan A1 - Jiajing Wang A1 - Benton H. Calhoun JF - GLSVLSI U1 - Ryan_GLSVLSI07.pdf|Ryan_GLSVLSI07.pdf ER -