@article {383,
	title = {A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs},
	journal = {J. Low Power Electron. Appl. (JLPEA)},
	volume = {6},
	year = {2016},
	author = {F. Yahya and H. Patel and Boley, J. and A. Banerjee and B. H. Calhoun}
}
@conference {350,
	title = {Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset},
	booktitle = {International Symposium on Quality Electronic Design},
	year = {2015},
	month = {03/2015},
	author = {Boley, J. and B. H. Calhoun}
}
@conference {342,
	title = {Modeling SRAM Dynamic VMIN},
	booktitle = {International Conference on IC Design and Technology (ICICDT)},
	year = {2014},
	month = {06/2014},
	author = {Boley, J. and V. Chandra and R. Aitken and B. H. Calhoun}
}
@article {339,
	title = {Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN},
	journal = {Journal of Low Power Electronics and Applications (JLPEA)},
	volume = {2},
	year = {2012},
	month = {04/2012},
	pages = {12},
	chapter = {143},
	author = {Boley, J. and J. Wang and B. H. Calhoun}
}
@booklet {272,
	title = {Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin},
	year = {2011},
	author = {Boley, J. and B. H. Calhoun and J. Wang}
}
