@article {339, title = {Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN}, journal = {Journal of Low Power Electronics and Applications (JLPEA)}, volume = {2}, year = {2012}, month = {04/2012}, pages = {12}, chapter = {143}, author = {Boley, J. and J. Wang and B. H. Calhoun} } @article {340, title = {Tracking On-Chip Age Using Distributed, Embedded Sensors}, journal = {Transactions on VLSI Systems (TVLSI)}, volume = {20}, year = {2012}, month = {11/2012}, pages = {12}, chapter = {1974}, author = {S. N. Wooters and A. C. Cabe and Z. Qi and J. Wang and R. W. Mann and B. H. Calhoun and M. R. Stan and T. N. Blalock} } @booklet {272, title = {Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin}, year = {2011}, author = {Boley, J. and B. H. Calhoun and J. Wang} } @article {275, title = {Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations}, journal = {Transactions on VLSI Systems (TVLSI)}, year = {2011}, author = {J. Wang and B. H. Calhoun} } @article {282, title = {Tracking On-Chip Age Using Distributed, Embedded Sensors}, journal = {Transactions on VLSI Systems (TVLSI)}, year = {2011}, author = {Stuart N. Wooters and A. C. Cabe and Z. Qi and J. Wang and R. W. Mann and B. H. Calhoun and M. R. Stan and Travis N. Blalock} } @article {69, title = {Impact of circuit assist methods on margin and performance in 6T SRAM}, journal = {Journal of Solid State Electronics}, volume = {54}, year = {2010}, note = {published}, month = {11/2010}, pages = {1398-1407}, publisher = {Elsevier}, chapter = {1398}, keywords = {Process variation, Read assist, Scaling, SNM, SRAM, Vmin, Write assist, Write margin, Yield}, url = {http://www.sciencedirect.com/science?_ob=ArticleURL\&_udi=B6TY5-50GTRCY-1\&_user=709071\&_coverDate=11\%2F30\%2F2010\&_rdoc=1\&_fmt=high\&_orig=search\&_sort=d\&_docanchor=\&view=c\&_acct=C000039638\&_version=1\&_urlVersion=0\&_userid=709071\&md5=2d0ef46bf2e72b91309a5c16}, author = {R. W. Mann and J. Wang and S. Nalam and S. Khanna and G. Braceras and H. Pilo and B. H. Calhoun} } @conference {calhoun-sub, title = {Sub-threshold Circuit Design with Shrinking CMOS Devices}, booktitle = {International Symposium on Circuits and Systems}, year = {2009}, month = {3/24/2009}, author = {B. H. Calhoun and S. Khanna and Mann, R. and J. Wang} } @conference {21, title = {Analyzing Static and Dynamic Write Margin for Nanometer SRAMs}, booktitle = {International Symposium on Low Power Electronics and Design}, year = {2008}, month = {08/2008}, pages = {129-134}, author = {J. Wang and S. Nalam and B. H. Calhoun} }