@conference {348,
	title = {Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories},
	booktitle = {VLSI Design Conference},
	year = {2014},
	month = {2014},
	author = {S. Khanna and S. V. Nalam and B. H. Calhoun}
}
@article {318,
	title = {A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications},
	journal = {Journal of Solid State Circuits},
	volume = {48},
	year = {2013},
	month = {01/2013},
	pages = {199-213},
	chapter = {199},
	author = {Yanqing Zhang and Fan Zhang and Yousef Shakhsheer and Jason D. Silver and Alicia Klinefelter and Manohar Nagaraju and James Boley and Jagdish Pandey and Aatmesh Shrivastava and Eric J. Carlson and Austin Wood and Benton H. Calhoun and Brian P. Otis}
}
@conference {278,
	title = {A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC},
	booktitle = {ISSCC},
	year = {2012},
	month = {02/2012},
	address = {San Francisco},
	author = {Fan Zhang and Yanqing Zhang and Jason Silver and Yousef Shakhsheer and Manohar Nagaraju and Alicia Klinefelter and Jagdish Pandey and James Boley and Eric Carlson and Aatmesh Shrivastava and Brian Otis and Benton Calhoun}
}
@article {257,
	title = {5T SRAM with Asymmetric Sizing for Improved Read Stability},
	journal = {JSSC},
	year = {2011},
	author = {Nalam, Satyanand and Benton H. Calhoun}
}
@conference {239,
	title = {Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM},
	booktitle = {Design Automation and Test Europe (DATE)},
	year = {2011},
	month = {03/2011},
	author = {S. Nalam and V. Chandra and R. C. Aitken and B. H. Calhoun}
}
@article {283,
	title = {Non-Random Device Mismatch Considerations in Nanoscale SRAM},
	journal = {IEEE Transactions of VLSI Systems (TVLSI)},
	year = {2011},
	author = {R. W. Mann and T. B. Hook and P. Nguyen and B. H. Calhoun}
}
@conference {37,
	title = {Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation},
	booktitle = {ISQED},
	year = {2010},
	pages = {139-146},
	author = {S. Nalam and V. Chandra and C. Pietrzyk and R. C. Aitken and B. H. Calhoun}
}
@article {69,
	title = {Impact of circuit assist methods on margin and performance in 6T SRAM},
	journal = {Journal of Solid State Electronics},
	volume = {54},
	year = {2010},
	note = {published},
	month = {11/2010},
	pages = {1398-1407},
	publisher = {Elsevier},
	chapter = {1398},
	keywords = {Process variation, Read assist, Scaling, SNM, SRAM, Vmin, Write assist, Write margin, Yield},
	url = {http://www.sciencedirect.com/science?_ob=ArticleURL\&_udi=B6TY5-50GTRCY-1\&_user=709071\&_coverDate=11\%2F30\%2F2010\&_rdoc=1\&_fmt=high\&_orig=search\&_sort=d\&_docanchor=\&view=c\&_acct=C000039638\&_version=1\&_urlVersion=0\&_userid=709071\&md5=2d0ef46bf2e72b91309a5c16},
	author = {R. W. Mann and J. Wang and S. Nalam and S. Khanna and G. Braceras and H. Pilo and B. H. Calhoun}
}
@conference {224,
	title = {Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress},
	booktitle = {CICC},
	year = {2010},
	month = {09/2010},
	address = {San Jose, CA},
	author = {Jiajing Wang and Nalam, Satyanand and Jerry Qi and R. W. Mann and Mircea Stan and B. H. Calhoun}
}
@conference {70,
	title = {Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers},
	booktitle = {Design Automation Conference (DAC)},
	year = {2010},
	month = {06/2010},
	pages = {138-143},
	author = {S. Nalam and M. Bhargava and K. Mai and B. H. Calhoun}
}
@conference {11,
	title = {Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T},
	booktitle = {CICC},
	year = {2009},
	pages = {709-712},
	author = {S. Nalam and B. H. Calhoun}
}
@conference {28,
	title = {An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization},
	booktitle = {TECHCON},
	year = {2009},
	abstract = {SRAM design in scaled technologies increasingly requires circuit innovations such as read/write assist techniques or alternative bitcells to ensure even basic functionality. However, the lack of a quick mechanism for understanding the impact of these circuit level changes on system level metrics makes accurate assessments of new circuit techniques difficult. Thus, we introduce Virtual Prototyper (ViPro), a tool that helps circuit designers explore this large design space by rapidly generating optimized virtual prototypes of complete SRAM macros. ViPro does this by allowing SRAM component specification with varying levels of detail {\textendash} from {\textquoteleft}black-box{\textquoteright} descriptions to complete netlists {\textendash} and by incorporating those components into a hierarchical model that captures circuit and architectural features of the SRAM to optimize a complete prototype. SRAM designers can use ViPro to generate base-case prototypes, which provide starting points for design space exploration, or to assess the impact of a low level circuit innovation on the overall SRAM design.},
	author = {M. Bhargava and S. Nalam and B. H. Calhoun and K. Mai}
}
@conference {36,
	title = {A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes},
	booktitle = {ICCD},
	year = {2009},
	pages = {523-528},
	author = {S. Nalam and M. Bhargava and Ringgenberg, K. and K. Mai and B. H. Calhoun}
}
@conference {21,
	title = {Analyzing Static and Dynamic Write Margin for Nanometer SRAMs},
	booktitle = {International Symposium on Low Power Electronics and Design},
	year = {2008},
	month = {08/2008},
	pages = {129-134},
	author = {J. Wang and S. Nalam and B. H. Calhoun}
}
@inbook {88,
	title = {Power Gating and Dynamic Voltage Scaling},
	booktitle = {Leakage in Nanometer Technologies},
	year = {2006},
	pages = {41-75},
	publisher = {Springer},
	organization = {Springer},
	author = {Benton H. Calhoun and James Kao, and Anantha Chandrakasan},
	editor = {Siva Narendra and Anantha Chandrakasan}
}
