@conference {4706,
	title = {A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications},
	booktitle = {32nd International Conference on VLSI Design},
	year = {2019},
	month = {01/2019},
	author = {Arijit Banerjee},
	editor = {Benton H. Calhoun}
}
@proceedings {4656,
	title = {Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications},
	journal = {Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED)},
	year = {2018},
	month = {07/2018},
	publisher = {IEEE},
	author = {Arijit Banerjee and Summanth Kamineni and Benton H. Calhoun}
}
@conference {364,
	title = {A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations},
	booktitle = {Custom Integrated Circuits Conference (CICC)},
	year = {2015},
	month = {09/2015},
	publisher = {IEEE},
	organization = {IEEE},
	address = {San Jose, CA},
	author = {Arijit Banerjee and Jacob Breiholz and Benton H. Calhoun}
}
@conference {330,
	title = {An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell},
	booktitle = {S3S},
	year = {2013},
	address = {Monterey, CA},
	keywords = {9T, bitcell, half-select-free, SRAM, Sub-VT, subthrehold},
	author = {Arijit Banerjee and Benton H. Calhoun}
}
