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Circuit Techniques for Lowering SRAM VMIN

We investigate the application of these peripheral assist methods to reduce the operating voltage of SRAM, called VMIN. Lowering VMIN helps to decrease power consumption and also keeps pace with the dropping logic VDD, allowing for easier integration. Large scale 6T SRAM beyond 65nm will increasingly rely on assist methods to overcome the functional limitations associated with scaling and the inherent read stability/write margin trade off.

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