Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS

This paper investigates the effect of body biasing on the leakage and delay of dynamic leakage suppression (DLS) logic. We present a brief theoretical analysis of the impact of body biasing on DLS logic as well as measurements from a test chip in 65nm CMOS. Results show that forward body biasing can reduce delay by up to 41X with negligible impacts on leakage.

Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS