In this work, we evaluate the impact of different peripheral write assist techniques, since the write operation limits voltage scaling, on the stability and energy of complete SRAM arrays operating in the sub-threshold region. The results of this characterization show that the best choice for a supply voltage and write assist combination varies based on the system level constraints and objectives.
Further, factors outside the cell such as half select stability dictate the optimal assist choice, the extent to which the assist should be applied, and the total array energy. Using data from a thorough study of assist options across supply voltage (VDD), we establish strategies for assist selection and array energy reduction based on system constraints. For example, the VDD lowering assist technique allows an array operation at 0.5V with the lowest possible energy of 8.5pJ when a longer delay is permitted, while negative bitline (NegBL) allows operation at the same voltage with 23pJ, but 121X faster write operation compared to VDD lowering.
While in the second phase, we investigate the use of combined read and write assist techniques to reduce the minimum operating voltage (VMIN) of the 6T SRAM bit-cell. While write failures initially limit VMIN, applying write assist introduces row and column half-select failures. Thus, read and write assist must be combined to allow scaling VMIN down to near/sub-threshold voltages. We find that combining negative bitline (BL) for write assist with array VDD boosting for read assist is most effective for reducing the array VMIN and eliminating half-select failures for commercial 130nm and sub-20nm FinFET technologies across different process corners and temperatures. The proposed combination results in the highest reduction in SRAM VMIN (to 300mV for FinFET and to 600mV for 130nm CMOS). This work also shows that controlling the degree of applied assist based on the chip corner will allow further reductions in VMIN for the 130nm CMOS (to 450mV) and the required assist needed to achieve VMIN for both the FinFET and the 130nm bit-cells.