Figure 1. The architecture of the closed-loop standby VDD scaling system.
Figure 2. The mechanism of the closed-loop standby VDD scaling system. VDD scaling is widely used to reduce SRAM leakage/active power. The minimum supply voltage (Vmin) during standby is determined by the worst value of the data retention voltage (DRV) in the presence of local variations, and it shifts with global variations. The conventional worst-case guard-banding approach selects a fixed standby VDD at design time to accommodate the variability of Vmin, which wastes substantial power for non-worst-case scenarios. We propose a canary-based closed loop VDD scaling system to achieve aggressive leakage power savings by tracking PVT variations through online canary cell monitors and robust feedback circuits that operate robustly at sub-threshold supply voltages. In addition, the system offers the flexibility to trade off between SRAM power reduction and yield improvement. Analytical models are derived to help tune the canary cells for a desired SRAM yield. We also propose several techniques to improve the effectiveness of the canary system, including the improvement of the canary replica cells, the new canary reset circuit, and the built-in self-test block to automating the calibration of the standby Vmin. Measurements from both the 90nm test chip and the 45nm test chip confirm the ability of the canary scheme to track global changes. Simulations with predictive technology models demonstrate that it promises to provide substantial standby power savings down to the 22 nm node.