VLSI Design Group


Search This Site

5T SRAM with asymmetric sizing in 45nm Bulk CMOS

This test chip is a part of the alternative bitcell exploration. It consists of a 32 kb 5-transistor (5T) SRAM bitcell that uses a novel asymmetric sizing approach to achieve increased read stability. The 32 kb SRAM is composed of two 16 kb SRAM blocks, each of which uses a different asymmetric sizing approach. A 16 kb 6T iso-area SRAM presents a reference point for comparison. The 5T and 6T arrays are divided into 4 kb blocks. The 5T SRAM uses full swing sensing for read, and VDD collapse and WL boost for write.

Measurements validate the design, showing read functionality below 0.5V. The 5T bitcell has lower write margin than the 6T, but measurements of the 45nm 5T array confirm that a write assist method restores comparable writability with a 6T down to 0.7 V. In addition to improved read stability, simulations demonstrate how the asymmetric sizing can be used as a knob to improve other critical metrics such as delay and leakage.