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45nm Bulk Test Chip for Enhanced Canary-based SRAM Standby VDD Scaling System

In this project, we propose several techniques to improve the efficiency of the canary based closed-loop standby VDD scaling approach. To improve the canary cell, we propose to add dummy bitcells around the canary cell so that it behaves like an SRAM cell in the presence of variation.We also propose a new canary circuit which always tunes the cell to its less-stable state to avoid the possibility that the canary cell would never fail. We incorporate a built-in self-test (BIST) block to automate the calibration of the worst SRAM data retention voltage (DRV) and the tuning of the initial failure threshold for adapting process variation. The 45nm test chip demonstrates the effectiveness of the canary approach in more advanced technologies. The measurement result also shows that the use of the dummy cells around the canary cell can reduce both local and global variation of the canary DRV.