This chip, designed using the MIT Lincoln Labs FDSOI 180nm technology, is intended to explore sub-VT SRAM and eDRAM. Alternative bit cells for sub-VT operation will be used with circuit assist approaches to determine the optimum conditions.
This chip, designed using the MIT Lincoln Labs FDSOI 180nm technology, is intended to explore sub-VT SRAM and eDRAM. Alternative bit cells for sub-VT operation will be used with circuit assist approaches to determine the optimum conditions.