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Putic, , B. H. Calhoun, . Di, . Lach, "Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design", International Conference on Computer Design (ICCD), ,, 01/2009. 2009_Putic_ICCD.pdf , 2009_Putic_ICCD_slides.pdf

Jurik, D, B. H. Calhoun, . Bolus, F. Weaver, N. Blalock., "Mobile Health Monitoring Through Biotelemetry", Bodynets, ,, 01/2009. Jurik_BodyNets2009.pdf

Calhoun, B. H, . Rabaey, "Optimizing Power @ Design Time - Memory", Low Power Design Essentials, ,, 2009.

Calhoun, B. H, . Rabaey, "Optimizing Power @ Standby - Memory", Low Power Design Essentials, ,, 2009.


Wang, , B. H. Calhoun, "Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond", IEEE Journal of Solid-State Circuits,volume = 43, ,, 11/2008. Wang_JSSC2008.pdf

Wang, , B. H. Calhoun, "An Enhanced Adaptive Canary System for SRAM Standby Power Reduction", TECHCON, ,, 09/2008.

Di, , B. H. Calhoun, . Putic, . Lach, "Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling", International Conference on Computer Design, pages 605-611, ,, 08/2008. Di_ICCD2008.pdf

Wang, J, S. Nalam, B H. Calhoun, "Analyzing Static and Dynamic Write Margin for Nanometer SRAMs", International Symposium on Low Power Electronics and Design, ,, 08/2008. Wang_ISLPED2008_paper.pdf , Wang_ISLPED2008_slides.pdf

Ryan, F, B. H. Calhoun, "Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation", International Symposium on Quality Electronic Design, ,, 03/2008. Ryan_ISQED2008_slides.pdf , Ryan_ISQED2008_paper.pdf

Calhoun, B. H, A. Rutenbar, . Yu Cao, . Mai, T. Pileggi, L. Shepard, "Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS", Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore\textquoterights Law),volume = 96, ,, 02/2008. CalhounEtAl_IEEEProc_08.pdf


Calhoun, B. H, . Chandrakasan, "A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation", IEEE Journal of Solid-State Circuits (JSSC),volume = 42, ,, 03/2007. Calhoun_JSSC07.pdf

Wang, , B. H. Calhoun, "Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM", Custom Integrated Circuits Conference (CICC), ,, 12/2007. Wang_CICC07_paper.pdf , Wang_CICC07_slides.pdf

Wang, , B. H. Calhoun, . Singhee, A. Rutenbar, "Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array", European Solid State Circuits Conference (ESSCIRC), ,, 12/2007. Wang_ESSCIRC07_paper.pdf , Wang_ESSCIRC07_slides.pdf

Wang, A, B. H. Calhoun, . Chandrakasan, . Verma, . Kwong, "Ultra-Dynamic Voltage Scaling for Energy Starved Electronics", Proc. of GOMAC Tech, ,, 12/2007.


Calhoun, B. H, . Chandrakasan, A. Wang, . Verma, "Sub-threshold Design: The Challenges of Minimizing Circuit Energy", International Symposium on Low Power Electronics and Design (ISLPED), ,, 10/2006. 2006_Calhoun_ISLPED.pdf , 2006_Calhoun_ISLPED_slides.pdf

Calhoun, B. H, . Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS", IEEE Journal of Solid-State Circuits (JSSC),volume = 41, ,, 07/2006. Calhoun_JSSC06_snm.pdf

Chandrakasan, P, B. H. Calhoun, . Verma, . Ickes, . Finchelstein, . Kwong, . Daly, "Micropower Wireless Sensors", NSTI Nanotech,volume = 3, ,, 05/2006. Chandrakasan_Nano06_submit.pdf

Calhoun, B. H, . Chandrakasan, "Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering", IEEE Journal of Solid-State Circuits (JSSC),volume = 41, ,, 01/2006. Calhoun_JSSC06_UDVS.pdf