Liu, N, R. Agarwala, "A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time", IEEE European Solid-State Circuits Conference (ESSCIRC), In Press.
Truesdell, D. S, B. H. Calhoun, "Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), In Press.
Boley, J, B H. Calhoun, "Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset", International Symposium on Quality Electronic Design, ,, 03/2015.
Klinefelter, , D. Wentzloff, B. Calhoun, . Zhang, . Shakhsheer, . Oh, . Roberts, A. Shrivastava, . Boley, . Akella, A. Roy, . Gonzalez, . Faisal, "A 6.45 μW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios", ISSCC, San Francisco, CA, IEEE, 02/2015. ISSCC_2015_klinefelter.pdf
Huang, Y, B H. Calhoun, A. Shrivastava, "A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), ,, 2015.
Calhoun, B H, D D. Wentzloff, "Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT", HOT Chips, ,, 2015.
Shakhsheer, Y, K. Craig, A. Shrivastava, D D. Wentzloff, N. Roberts, S. Wooters, "Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors", GOMACTech, ,, 2015.
Shrivastava, A, K. Craig, N. Roberts, "A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems", EEE International Solid-State Circuits Conference (ISSCC), ,, 2015.
Boley, , B. H. Calhoun, . Beshay, "Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization", Transactions of Very Large Scale Integration Systems, ,, 2015.
Zhang, Y, B H. Calhoun, "Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits", International Symposium on Quality Electronic Design (ISQED), ,, 04/2014.
Banerjee, A, B H. Calhoun, M. Sinangil, J. Poulton, C T. Gray, "A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs", International Symposium on Quality Electronic Design (ISQED), ,, 04/2014. 06783299.pdf
Klinefelter, A, B H. Calhoun, "A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs", S3S Conference, Monterey, CA,, 10/2014. s3s_final_klinefelter_0.pdf
J.Bolus, , B H. Calhoun, . T.Blalock, "39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation", Journal of Low Power Electronics and Applications (JLPEA),volume = 4, ,, 09/2014.
Beshay, , B. H. Calhoun, . Chandra, . Aitken, "A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM", ISLPED, ,, 08/2014.
Boley, J, V. Chandra, R. Aitken, "Modeling SRAM Dynamic VMIN", International Conference on IC Design and Technology (ICICDT), ,, 06/2014.
Banerjee, A, B H. Calhoun, "An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications", Journal of Low Power Electronics and Applications (JLPEA),volume = 4, ,, 05/2014.
Shrivastava, A, B H. Calhoun, D. Wentzloff, "A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting", IEEE Custom Integrated Circuits Conference (CICC), ,, 07/2014. 2014_Aatmesh_CICC.pdf
Arrabi, S, B H. Calhoun, K. Skadron, D. Moore, L. Wang, "Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems", International Symposium on Field-Programmable Custom Computing Machines (FCCM), ,, 07/2014. 06861633.pdf
Granacki, J J, B H. Calhoun, A R. Dasu, M. Jagasivamani, L. McIlrath, M. Fritze, "LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications", GOMAC Tech, ,, 07/2014.
Shrivastava, A, S. Khanna, B H. Calhoun, Y K. Ramadass, S. Bartling, "A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages", Symposium on VLSI Circuits, ,, 07/2014. 06858364.pdf
Khanna, S, B H. Calhoun, S V. Nalam, "Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories", VLSI Design Conference, ,, 07/2014. 06733120.pdf
Craig, , B. H. Calhoun, . Khanna, . Lach, . Shakhsheer, . Arrabi, "A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance", Journal of Solid State Circuits, ,, 2014. 06665019.pdf
Beshay, P, B H. Calhoun, V. Chandra, R. Aitken, "Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM", Design Automation Conference (DAC), ,, 2014.
Zhang, , B. H. Calhoun, "Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method", S3S Conference, Monterey, California,, 10/2013. Zhang_S3S2013.pdf
Boley, , B. Calhoun, . Beshay, "Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization", SRC TECHCON, ,, 09/2013.
Beshay, , F. Ryan, B. H. Calhoun, "A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers", Journal of Low Power Electronics and Applications, ,, 05/2013. Beshay_JLPEA13.pdf