Ultra Low Power SRAM Design and Characterization of the impact of different device types

This work characterizes the impact of different types of devices (High Vt, Standard-Vt, and Multi-Vt) in an 8T SRAM bitcell for various sub-threshold metrics. After studying in-depth analysis under the process and temperature variation, a 2KB of SRAM is fabricated. The SRAM design includes two banks of 1KB each with two optimal bitcells from the previous comparison. The measured results from a commercial 130 nm chip show that the proposed array consumes a minimum of 6.24 pJ/access with a 17.16 nW standby power at 400 mV.

Publications:
Patel, H., F. Yahya, and B. Calhoun, "Optimizing SRAM Bitcell Reliability and Energy for IoT Applications", International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, IEEE, 2016.
Yahya, F., H. Patel, J. Boley, A. Banerjee, and B. H. Calhoun, "A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs", J. Low Power Electron. Appl. (JLPEA), vol. 6, issue 2, 2016.

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