Subthreshold Processors

This work presents an implementation of a 16-bit MSP430 processor for ultra-low-power (ULP) systems catering to battery-less wireless sensor nodes, biomedical, and other IoT applications. Implemented in a custom extremely low power (xLP) 90nm FDSOI process, the processor consumes 1.3μW operating at 0.4V while executing a peak detection algorithm at 250 kHz. It supports the standard MSP430 instruction set architecture (ISA) and demonstrates QRS peak detection for an Electrocardiogram (ECG) application. The measured energy while executing peak detection at 250 kHz was 5pJ per cycle at 0.4V. The fabricated xLP devices show 55% reduction in threshold voltage (Vth) variation compared to similar-sized transistors in a traditional FDSOI process.

The increasing focus on IoT specific applications such as wearable sensors, portable biomedical electronics such as ECG monitors, and self-sustaining surveillance systems demand energy-efficient system operation. Owing to their requirements of having a smaller form-factor and mostly self-powered near-perpetual operation for a longer system lifetime, such systems are severely energy-constrained. Within the limited energy budget, these systems need to run application specific programs and sub-routines such as ECG monitoring. Hence, energy-efficient processing at the circuit and at the system level is essential to minimize the energy per operation of such systems. Existing work in literature has reported systems or processor implementations consuming nW to μW power levels by operating the system near the threshold voltage (Vth) of a transistor.
Operating a digital circuit in the subthreshold regime causes transistor leakage to be a dominant source of energy consumption because of exponentially large delays. Hence optimizing the leakage characteristics of a device can result in significant benefits at the overall system level. However low voltage transistor operation presents four key challenges: 1) to minimize the subthreshold swing and achieve maximum ON current below threshold, 2) to minimize static leakage current, 3) to minimize Vth variation, and 4) to minimize device capacitances. The extremely low power (xLP) FDSOI process provides CMOS transistors, optimized for lower subthreshold leakage with reduced Vth variation and minimal degradation in performance.

In this work, we implement a 16-bit MSP430 processor for subthreshold operation for diverse IoT applications in the 90nm xLP FDSOI process using logic synthesis and auto-place-and route (APR) tools. A library of logic gates and sequential circuits such as flip-flops and latches were characterized to operate at 0.36V, and timing closure was achieved at 200 kHz using static-timing-analysis (STA) tools. Measurement in silicon shows an energy consumption of 5pJ/cycle at 0.4V running a QRS peak detection algorithm on an ECG data at 250 kHz on the processor.

Publications

Roy, A., P. Grossmann, S. Vitale, and B. Calhoun, "A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications", International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, IEEE, 2016.

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