Circuit Robustness to Power Supply Variation in Low-Voltage Latch and Register-Based Digital Systems

This work compares the impact of power supply variation on the performance of register-based and latch-based digital circuits. A 32-tap, 16-bit FIR filter is fabricated using both flip-flops and latches in a 130nm CMOS process. Measurements show 25-37% improvement in energy-efficiency for the latch-based implementation operating below 0.6V subject to 44-120mV, 1 kHz peak-peak VDD ripple. This work also presents a low-power, low-frequency droop measurement technique using digital circuits, which consumes 0.9μW at 0.75V.

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