Pre-design Modeling and Analysis

A fine-grained GALS design methodology is one in which the SoC is partitioned into a large number of synchronous sub-blocks, each spanning no more than a few mm^2 of physical area and operating with its own local clock. The insertion delay for such small synchronous islands is only a few hundred picoseconds. Due to the close proximity of the clock generator and load circuits, they also tend to experience similar voltage fluctuations. Hence, fine-grained GALS adaptive clocks can reduce the effect of insertion delay and spatial workload variations and the additional margins associated with them. SPICE and Verilog-A is the modeling platform used to quantify the effect of clock-tree insertion delay and spatial workload variations on power supply noise tolerance and to compare between traditional synchronous adaptive clocking and a fine-grained GALS adaptive clocking scheme.

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